Principles of Secure Processor Architecture Design (Record no. 1111)

MARC details
000 -LEADER
fixed length control field 00413nam a2200145Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 200312s9999||||xx |||||||||||||| ||und||
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781681730011
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004.22
Item number Sze
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Szefer, Jakub
9 (RLIN) 723
245 #0 - TITLE STATEMENT
Title Principles of Secure Processor Architecture Design
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. USA
Name of publisher, distributor, etc. Morgan and Claypool Publishers
Date of publication, distribution, etc. 2019
300 ## - PHYSICAL DESCRIPTION
Extent xxi, 151p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer Architecture
9 (RLIN) 724
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Books
Holdings
Withdrawn status Lost status Damaged status Not for loan Collection code Home library Current library Source of acquisition Cost, normal purchase price Total Checkouts Full call number Barcode Date last seen Date last checked out Copy number Price effective from Koha item type Public note
      Reference Technical IIT Goa Central Library IIT Goa Central Library Technical Bureau India Pvt. Ltd. 4964.00 1 004.22/Sze 3276 2021-01-25 2020-07-02 1 2020-03-12 Reference TB1698|| 17-12-19|| 25.00%|| USD 69.95